About this Fundamentals section
The reader The Cambrian Explosion of Chips explained the instruction set (ISA) as an “invisible contract.” But a contract needs a “machine” to actually carry it out. This Fundamentals section explains what that machine is, and — building it up as blocks on a desk — looks in plain terms at how the machine moves. Registers, the ALU, the five-step flow, CISC and RISC, RISC-V’s low power and modular ISA — and finally, “what we ourselves need to decide when we build our own chip.” It is the piece that bridges the space between the reader (the contract) and the four courses (doing the work).
This is not one of the “intro courses.” KiCad / FPGA / LibreLane are hands-on intro courses (labeled “Basics 01–03” in the series). This Fundamentals section is not a course but the groundwork you read beforehand: “how a CPU works, and what you get to choose.” You write no code and draw no schematics. Read it right after the reader and before starting the intro courses, and the “point” of the work in each course comes into much clearer view.
Preface: What is “computer architecture,” really?
Is “architecture” the contract, or the machine? We untangle it into three layers — and then: the five-step flow is a problem largely settled back in 1985. So we don’t redesign it; we “choose, assemble, and check.” A first look across what this Fundamentals section is really about.
Read this chapterChapter 1: What a register is — the CPU’s workbench close at hand
Why is a “place to remember” needed at all? The difference between the warehouse (memory) and the workbench (registers), bit width, and RISC-V’s 32. Because the workbench is small, an instruction becomes “load, compute, store.”
Read this chapterChapter 2: The blocks that make up a CPU — a parts catalog
Lay the blocks on the desk. ALU, register file, program counter, control unit, instruction decoder, memory, clock. “What’s there, and why it’s needed.” Put them together and you have one CPU.
Read this chapterChapter 3: How an instruction runs — five steps and the assembly line
Fetch → decode → execute → memory access → write-back. Why it can’t happen all at once but is split into steps. What the assembly line (pipeline) really is, and why it becomes “an eye for choosing and a map for debugging.”
Read this chapterChapter 4: CISC and RISC — a complex instruction, or a stack of simple ones
How much work do you pack into a single instruction? The upside of multi-function instructions, and the cost of a heavier machine. The two design philosophies behind the choice of “why a RISC-V core.”
Read this chapterChapter 5: MIPS — the RISC textbook, ancestor of RISC-V
RISC sprouted at Berkeley and Stanford. Why did MIPS become “the textbook”? The tollgate of a commercial ISA, and its lesson. From MIPS to RISC-V — the story of a shared language opened up.
Read this chapterChapter 6: Low power — how the way you write the contract bears on power
What “low power” really is: the fewer transistors that switch, the less it eats. Simple instructions keep the decoder light. Load only what you need. Clock and power — though in practice it depends on the implementation and the use.
Read this chapterChapter 7: What “combining modules” really means
Separate the two “modules”: ① the hardware parts (ALU, FPU) and ② the ISA vocabulary (RV32I + extensions). Add an extension and you need the matching part — which is why you can build “a chip with just what you need.”
Read this chapterChapter 8: The extension catalog — what’s there, and what for
The RV32I base, M for multiply, A for atomic, F/D for floating point, C for compressed. What RV32IMAC means. Choosing extensions from the use — your own chip’s “menu.”
Read this chapterChapter 9: The “decisions sheet” for your own chip
Core, pipeline stages, extensions, memory, peripherals/bus, clock, process, verification. The judgment material learned in this Fundamentals section, gathered into a single table. This is the map for the design decisions you make as “commander.”
Read this chapterClosing chapter: This is how an instruction set gets designed
Now that you’ve seen the machine, the shape of the ISA reveals its “reasons.” The reader (the contract) and the Fundamentals (the machine) connect here. Next comes doing the work — toward what it means to watch PicoRV32 run in the FPGA course.
Read this chapterBefore you read this Fundamentals section
This piece is prepared as shared groundwork to read after the reader The Cambrian Explosion of Chips and before moving on to the four courses. For the sake of accessibility, some details are deliberately simplified. Core types and performance, and the moves of individual companies, update and shift quickly, and readings differ by viewpoint. The text tries not to fix specific numbers or firm assertions; please check primary sources yourself for anything that catches your interest.
※ The first draft is June 2026. The content is updated as it is checked. When the urge to “try building one” catches fire, head to Chip Makers (the four courses).