Chapter 1　What a register is — the CPU’s workbench close at hand

1.1 Why a “place for intermediate values” is needed at all

As we saw in the reader, a CPU was “a part that computes.” For example, “add 3 and 5, then multiply that answer by 2.” By hand, you first get 3+5 = 8, then keep that 8 in mind for a moment, then compute 8×2 to get 16. Without a place to “keep it in mind for a moment,” you can’t pass the addition’s answer to the multiplication, and the computation can’t advance a single step.

A CPU is exactly the same. It needs a place to set intermediate values, for just an instant, right within reach. That holding place is the register.

1.2 The register as a holding place — the kitchen’s “workbench cell”

If we liken a register to a kitchen, it’s the cell on the workbench at the cook’s hand. A value being computed is set down for a moment on a cell right at hand, without going all the way to a distant warehouse. Take it out at once, rewrite it at once — that is a register’s role. This chapter takes that workbench apart, carefully.

1.3 [Core] Separate the three easily-confused numbers and understand them

This is the most important, and most easily confused, point. In talking about registers, “32” comes up twice, and they are different things. Don’t rush; split it into three layers.

• The workbench is one. A kitchen has just one workbench. This, for the whole CPU, is called the register file.
• On it, 32 cells. The workbench is partitioned, with 32 cells lined up. One of these cells is a register. The cells have names: x0, x1, …, x31. For instance “x1” is a name meaning “cell number 1,” not 0 or 1.
• Inside one cell, 32 squares. Peer further inside the cell, and there are 32 squares — small frames, like little dishes, each holding one 0 or 1. This row of 32 represents a single number. This is “32 bits,” and since a square is 0/1, it’s binary.

To sum up — one workbench, 32 cells, 32 squares. “1 · 32 · 32” are numbers at different levels. x1 is a name, the content is 32 of 0/1, the base is binary. They mix up easily, so keep these three apart.

1.4 A cell’s name is an “address” — a number pointing to which cell

The cell names x0–x31 are actually addresses. When an instruction says “add x1 and x2 into x3,” x1, x2, x3 are numbers pointing to “which cell.” Since there are only 32 cells, the numbers 0–31 suffice (a very small number). So an instruction can name “which cell” in just a few digits. Compared later with the warehouse (memory) addresses, you’ll see this “smallness” ties into a register’s speed.

Now let’s look with a designer’s eye. Why 32 cells? It’s the result of a tug-of-war. Too few, and there aren’t enough places for values, so round trips to the warehouse (memory) increase and it slows down. Too many, and the digits to express a cell’s name (number) increase, so instructions fatten and the circuit grows. With 32, a number can be named in exactly 5 digits (5 bits) and it’s enough as a holding place — around this “just right” spot, RISC-V settles on 32. Design is choosing the balance in such a tug-of-war.

1.5 x0 is always zero — why a fixed 0 pays off

Of the 32 cells, only x0 is special. Its content is fixed at 0 always; whatever you try to write, it doesn’t change, and reading it always gives 0. It looks wasteful at a glance, but having it makes instructions tidy. For example —

• You can make a copy. “x3 = x5 + x0” just adds 0 to x5 = a copy of x5. No dedicated copy instruction needed.
• It becomes a discard. Write unneeded results to x0. Since x0 doesn’t change, they simply vanish.
• You can make “do nothing” too. An instruction that writes to x0 = effectively nothing happens (the so-called NOP).

Just having one zero-only cell pays off this much. In return, the freely usable ones are 31 of 32. The squares side (a cell’s capacity = 32 bits) can be used in full. “The number of cells is 32, but usable is 31” and “the squares (bit width) are the full 32” — the trick is not to mix these two.

1.6 The difference from the warehouse (memory) — so an instruction becomes “load, compute, store”

“If it’s just placing values, there’s memory (RAM) too — why do we need cells separately?” Because speed and nearness are completely different. The workbench cell is at hand and can be taken in an instant — but there are only 32. The warehouse (memory) can hold any number, but is far, and fetching keeps you waiting several beats. It’s the same for addresses: with 32 cells the number is short and can be named at once; the warehouse has vast shelves, so addresses are long, and fetching is far.

A CPU’s computation is furiously fast, so if it made a round trip to the warehouse each time, the very hand that computes (the ALU) would end up idle, waiting. So just the few values in use now are kept on the cells at hand. From here, computation naturally takes the following three-beat rhythm.

• Load. Bring the values in use now from the warehouse (memory) to the workbench (cells).
• Compute. Pass the cell values to the ALU, compute, and return the result to a cell again.
• Store. Put values that are done with back from the cells to the warehouse.

In the kitchen, it goes like this. Take the instruction “combine x5 and x6, and place it in x7,” and liken it to making stew. Cell x5 already holds prepped onions, cell x6 holds carrots (the 0/1 of the squares note down “which ingredient, and how much”). As the instruction directs, the stove (ALU) reads and combines the contents of x5 and x6, gives it one simmer, and serves the result into the destination cell x7. At this point —

• The ingredient cells don’t decrease. The onion cell (x5) and carrot cell (x6) are only read. Even after being used in the dish, their contents remain as they were.
• The destination is only the one named cell. The result is served into the cell the instruction named, x7. Whatever x7 held before is discarded, and its 32 squares are wholly replaced with the new value.
• Read two, write one. It’s not “we combined two cells, so we split it back into two.” Read two cells, write the result to one cell — this is the basic shape of computation.

That RISC (and RISC-V) instructions divide roles crisply into this “load / compute / store” is no accident. The physical circumstance that the workbench is small determines the very shape of the instructions. This rhythm shows itself clearly once more in Chapter 3’s “five steps.”