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Chapter 9 The “decisions sheet” for your own chip

The aim of this chapter. By here, the judgment material has come together. This chapter is the grand summary. We line up the “things to decide” learned in this Fundamentals section on a single sheet. Core, extensions, memory, clock, number of stages, verification — for each, we make a map that lets you view at a glance “what · what you decide it from · where in this book you learned it.” This is the starting point when, as “commander,” you make design decisions.

9.1 The decisions sheet

Gathering onto one sheet the judgments that came up throughout the Fundamentals section, it looks like this. In this Fundamentals section, where we write no code and no schematics, what we’ve gained is this “map of what to decide.”

Your own chip: the decisions sheet A correspondence table of what to decide, what the judgment is based on, and the book's chapters. Core is by the numbers handled and memory breadth, Chapter 1. Extensions by the computation the use needs, Chapters 7 and 8. Memory layout Chapter 2. Clock and voltage by the tug-of-war of speed and power, Chapters 2 and 6. Number of stages by the balance of speed and area and power, Chapter 3. Verification from simulation to real hardware, to the courses. What to decide Basis (what you decide it from) Book Core (base) RV32I / RV64I — by numbers handled · memory breadth Ch. 1 Extensions M / A / F / D / C — by the computation the use needs Ch. 7·8 Memory layout how to split instr./data · capacity · I/O Ch. 2 Clock · voltage tug-of-war of speed and power (measured by STA) Ch. 2·6 Stages (pipeline) balance of speed and area/power Ch. 3 Verification simulation → check on real hardware courses
The judgment material learned in this Fundamentals section, onto one sheet. From the left: “what to decide,” “what you decide it from,” “where in this book you learned it.” This is the map for “choosing and assembling” your own chip.

9.2 How to read the sheet

Each row is something we looked at one by one in the previous chapters. The core (base) is from the size of the numbers handled and the breadth of memory (Chapter 1). Extensions are from the computation the use needs (Chapters 7·8). Memory layout is from how you place instructions and data (Chapter 2). Clock and voltage are from the tug-of-war of speed and power, and that length is measured by timing analysis (Chapters 2·6). Stages are from the balance of speed and area/power (Chapter 3). And verification goes from simulation to real hardware — from here on, it’s the domain of the hands-on courses.

9.3 These are not independent — a “tug-of-war”

What matters is that these are not separate choices. Speed, area, power are always in a tug-of-war relationship. Raise the clock and it’s fast but eats power. Add extensions and it’s high-function but parts increase. Split the stages finer and it’s fast but the circuit grows. Attack one, and another moves. Design is, within this tug-of-war, choosing a single point that fits the use — not invention from zero, but choose, assemble, and check. That is the answer to “what do we decide,” repeated since the preface.

Which decision is this knowledge for. This single sheet is the map of your own chip’s design decisions. You could say it’s the preface’s “decisions map” brought down into concrete items. In the next closing chapter, with the eye that has looked at the machine up to here, we look back once more at the shape of the instruction set (contract). Then its shape reveals its “reasons” — the reader (contract) and the Fundamentals (machine) connect there into one.