Closing chapter　This is how an instruction set gets designed

C.1 Because we’ve seen the machine, the contract’s shape shows its “reasons”

In the reader, we received the instruction set (ISA) as an “invisible contract.” Why are RISC-V’s instructions so simple, so even-grained, with roles split into load/store — at the time, that was “just the agreement.” But now that we’ve seen the machine, we can tell. That shape was the flip side of the machine’s circumstances.

• Because the workbench is small, load/store type. There are only 32 cells (Chapter 1). So it can only “load from the warehouse, compute at hand, store back.” That the contract splits load/store is a copy of this physics.
• Because it mustn’t disturb the assembly line, simple and even-grained. If instructions were of scattered sizes and efforts, the five steps would jam (Chapter 3). So the contract makes instructions uniform and simple.
• Because it wants to keep the machine small, only as much as you need. Add vocabulary and you need parts (Chapter 7). So the contract is modular, base + extensions.

So, this is how an ISA gets designed. The contract itself is shaped to lean toward a form the machine can carry out without strain, fast, and low-power.

C.2 The reader (contract) and the Fundamentals (machine) connect here

In the preface we said “contract and machine are separate.” That’s correct. But they are not unrelated. The contract is designed into a form the machine can carry out. So the reader’s “why this shape” for the contract, now that we’ve seen the machine, drops right into place.

C.3 What do we decide?

Once more, back to the first question. “For our own chip, what do we decide?” The answer has been the same since the preface. Not to invent from zero, but to choose, assemble, and check. Choose a core, assemble extensions, estimate clock and power, and confirm by verification. That map is Chapter 9’s decisions sheet. Share the contract (RISC-V), choose the machine (low-power, or high-performance) — what this Fundamentals section has given you is that “eye for choosing.”

C.4 Next, you do the work

Up to here, by reading, we’ve looked at how a CPU works and what you decide in design. Next, it’s the “build” turn. In the FPGA course, PicoRV32, a small RISC-V core, actually runs. Looking at it with an eye that has passed through the Fundamentals, you should see “now a value has been placed on the workbench,” “now the assembly line has moved” — its “meaning as it runs” becomes clear. The Fundamentals section was the entrance for that.