English / 日本語
← Back to the Fundamentals home Chapter 4: Part 2 · How you write the contract changes the machine

Chapter 4　CISC and RISC — a complex instruction, or a stack of simple ones

The aim of this chapter. At the end of Chapter 3, we said, “the more even the grain of instructions, the less the assembly line jams.” Over how to even that grain, the CPU world has long had two ways of thinking. CISC and RISC. In this chapter we pin down the difference between the two, and the merits and costs of each. And — we confirm, in concrete form, the preface’s point that how you write the contract (the instruction set) largely determines the build of the machine that carries it out.

4.1 Two design philosophies — how much do you pack into one instruction

The fork is a single point. How much work do you pack into one instruction. The style of packing in a lot is CISC; the style of keeping it few and simple is RISC. Even to make it do the same computation, how you write the contract (the instruction set) diverges greatly here.

4.2 CISC — with one instruction, a lot of work

First, the packing side. CISC (Complex Instruction Set Computer) is the idea of “with one instruction, settle as much work as possible.” For example, “fetch A and B from memory, multiply them, and return the result to memory” — this whole sequence can be handled by just one instruction.

The merit is easy to see. You can write programs short, and the number of instructions needed is small too. In an age when memory was expensive, this was a great virtue.

There are costs too. Since one instruction moves through several actions inside, the decoder that reads it grows complex, and the instruction lengths become uneven too. Seen with Chapter 3’s assembly-line eye, the amount of work per step isn’t even, and the belt doesn’t flow smoothly. Just as you wrote the contract “rich,” the machine that carries it out grows heavy. The representative is x86, familiar from PCs.

4.3 RISC — simple instructions, many, fast

The other is the style of keeping instructions simple. RISC (Reduced Instruction Set Computer) is the idea of “let one instruction do only a very simple job.” For the earlier “multiply A and B and return to memory,” RISC splits this into four small instructions: “fetch A / fetch B / multiply / store.”

The number of instructions increases. But each one is simple, and the lengths are even. So the decoder is light, and the pipeline flows smoothly. The rhythm of “load, compute, store” seen in Chapter 1 — the discipline that only load and store touch memory, and computation happens only on the registers — was exactly this RISC manner.

The most familiar RISC today is ARM — widely used in smartphones, tablets, and embedded devices — and RISC-V, the one this series deals with. Many of the devices in your palm carry this RISC blood. If the earlier x86 is the representative of CISC, then ARM and RISC-V are the representative RISCs — placing that on the map makes the story ahead clearer. (Their origins, and the difference over who “owns” the contract, we trace in the next Chapter 5.)

The difference in grain between CISC and RISC The same job of "multiply A and B and return to memory": CISC packs four steps inside one instruction. RISC splits it into four simple, even-length instructions: fetch a value, fetch a value, multiply, store. CISC — pack into 1 instruction RISC — line up simple instructions = just one instruction fetch a value fetch a value multiply store ① fetch a value ② fetch a value ③ multiply ④ store One instruction. But heavy inside, uneven in length. Four instructions. But each light, even in length.
Same job, two ways to write the contract. CISC packs it into one instruction (left); RISC lines up simple instructions (right). RISC has more instructions, but each is light and even in length, so it suits the assembly line.

4.4 One bit of backstory — today’s CISC also breaks things down RISC-style inside

“So is CISC obsolete?” — not so simple. Today’s x86 chips are said to, inside, first break down the complex instructions they receive from outside (the CISC contract) into simple, small operations like RISC’s, before executing. That is, the outward contract stays CISC and keeps compatibility, while the inner machine takes in RISC-style merits.

Here too, the preface’s point comes into play. The contract (the outward appearance) and the machine (the inner build) are separate things. The same contract can be carried out by quite different machines — that freedom appears in a place like this too.

4.5 Summary — how you write the contract determines the build of the machine

It’s not a matter of which is right. It’s a difference of design philosophy — what to prioritize. And what matters is that how you write the contract (the design of the instruction set) determines, to a considerable degree, the build of the machine that carries it out. In the next Chapter 5, we visit MIPS, which first put this RISC way of thinking into textbook form and became the ancestor of today’s RISC-V.

Which decision is this knowledge for. The core you use in your own chip is now, in most cases, RISC — above all RISC-V. The reason is just as in this chapter: simple, even-grained instructions let the machine be small and light, are easy to implement and verify by your own hand, and are docile to the pipeline. Once the difference between CISC and RISC settles in, you can explain “why choose a RISC-V core” in your own words. Choosing the “Brain” in the preface’s “decisions map” — its reasoning is here.