Chapter 6: The transistor went 3D ― "2 nm" isn't a line width

Up to here, the story has been mainly about "design (the language)." In this chapter, we turn to the "body" of the chip itself — that small switch (the transistor) we saw in Chapter 1. In fact, over the last few years, the transistor has changed shape greatly, from flat to three-dimensional. And the number familiar from the news, "2 nm (2 nanometers)," no longer means the old kind of "thinness." Let's cleanly unmask the point a newcomer is most easily fooled by.

6.1 "2 nm" — what exactly is 2 nm?

The news says "the latest chips are 2 nm." Most people take it this way: "the circuit lines have gotten as thin as 2 nanometers." A nanometer is one-billionth of a meter. A dizzying thinness. — But this is, strictly, wrong. Today's "2 nm" no longer refers to a line width. "Eh? Then what is the number?" To solve that riddle, let's go back through a little history.

6.2 Long ago, the number = the real thinness

The history of chip-making was long a single road of "thinner, smaller, at all costs." Make the circuit lines thinner, and you can pack more switches into the same area — faster, more efficient. This flow of "packing in ever more" supported the progress of semiconductors (what you often hear called "Moore's law" is, roughly, this "momentum of packing in").

And once, the node number (the ◯◯ nm) corresponded roughly to the actual dimensions. Up to, say, the "32 nm" of a generation ago, that number more or less reflected reality as a guide to how thin the circuits were. So back then, "smaller number = truly thinner = impressive" was broadly correct. The trouble starts from here on.

6.3 Flat hit a limit ― so the transistor "stood up"

Once the pursuit of thinness crossed a certain line, a problem arose. The switch stopped turning fully "off." Make it too small, and the electricity you thought you'd cut off leaks a little. Leakage produces heat and wasted power, and drags down performance. The flat (planar) transistor hit its limit here.

So engineers changed their thinking. "If flat won't do, make it three-dimensional." In the early 2010s, a new structure appeared that stood the transistor's channel (the path) up vertically, like a fin. This is FinFET. With the switch's "gate" surrounding the raised fin from three sides, leakage could be held down sharply. This was the first step of the transistor going from flat to three-dimensional.

To put it another way, an image of raising the embankment. On a flat rice paddy, water seeps out. So make the ridge a three-dimensional embankment and press it in from three sides, and you can firmly stop the water (electricity) from leaking. FinFET is like giving the transistor a "three-dimensional embankment."

6.4 Further evolution ― stacking boards, "GAA / nanosheet"

But as things got thinner still, even that "surround from three sides" FinFET could no longer hold back the leakage. So came the lead of today's 2 nm generation ― GAA (gate all around), also called nanosheet. The name sounds hard, but the idea is clear. Stack a few thin boards (sheets), and have the switch's "gate" surround each one from all around (all four sides).

From three sides (FinFET) to all around (GAA). The more perfect the surround, the better the control of electricity, and the more the leakage is suppressed. This is called the biggest turn in transistor structure in more than ten years. Companies compete over what to call it — TSMC says "nanosheet," Samsung "MBCFET," Intel "RibbonFET" — but the underlying idea is shared.

   The transistor's "3D" triple jump (evolution to suppress leakage)
 ───────────────────────────────────────────────────────────────
   (1) planar          gate from above only    ... shrink it and it leaks (the limit)
        |
   (2) FinFET (fin)    gate surrounds from three sides   ... from the 2010s. the first 3D step
        |
   (3) GAA / nanosheet gate surrounds from all around    ... the 2 nm generation. stacked boards
 ───────────────────────────────────────────────────────────────
   The more you increase the surround, the better the switch's "cut-off," and the less it leaks.

6.5 So "2 nm" is no longer a line width

Back to the first riddle. Since the transistor has changed its whole make — flat -> 3D -> stacked — you can no longer measure a generation with the single yardstick of "line width." As a result, today's "2 nm" is not a word for a specific dimension (a line width); it's a brand name, a generation name, for "this generation's technology."

The driving force behind the shrinking number has changed, too. From the single push of "make the lines thinner," the decisive ground has moved toward rebuilding the structure into three dimensions, and packing cleverly. So the march of numbers, "after 3 nm comes 2 nm, then…," is best viewed less as a record of "thinness" and more as a count of "generations."

6.6 The 3D shift isn't stopping

The transistor's move to three dimensions doesn't end here. Next are further three-dimensionalizations: stacking two kinds of transistor one above the other (CFET), and feeding electricity from the back of the chip (backside power delivery). Beyond the transistor tier, ways of making are also spreading: stacking chips themselves several high (3D stacking), and combining small chips with different roles, the "chiplet." From the age of "spreading things flat across a board" to the age of "building up, three-dimensionally." The chip is becoming, quite literally, three-dimensional architecture.

6.7 This chapter's summary, and the bridge to the next

• The transistor went 3D. Flat -> fin (FinFET) -> stacked boards (GAA / nanosheet). The more the gate surrounds, the more leakage is held down.
• "2 nm" is no longer a line width. It's now a "brand name for a generation." The real dimensions are larger. Read the number as "the signboard of the latest generation."
• The 3D shift continues. Stack the transistors, feed power from the back, stack whole chips — the chip goes to three-dimensional architecture.

Up to here, the story was about what shape to make the transistor, that "body." But how is that precise shape "drawn into the silicon in the first place"? In fact, a shift is happening in that "way of drawing," too. The conventional way starts from carving a "stamp (the master)"; now research into "maskless" methods, which remove that gate, is advancing. The next chapter, Chapter 7, is about a shift in the way of making itself — the manufacturing-side upheaval that pairs with the opening-up of design.